1. Hiring: Physical Design

・2+ years of experience in Physical Design (Backend).
Experience in Auto P&R flow and Timing Closure... with 45nm and below technologies.
Have EDA tools experience for Physical Design of Synopsys/ Cadence/Mentor... such as Innovus/ICC2, Primetime/Tempus, Calibre,...
Good scripting skill (Tcl/ Cshell/ Perl...)
Self-motivator with good problem-solving skills.
Good English or Japanese communication skill.


2. Hiring: Analog & AMS IC Design

2+ years of experience in Analog Integrated Circuit (IC) design.
Experience designing analog circuits such as bandgap references, operational amplifiers, comparators, regulator.
Experience with SerDes sub-circuits: receive equalizers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator is a plus.
Familiar with Cadence simulation tools.
Knowledge of layout effect (matching, parasitic effect).
Self-motivator with good problem-solving skills.
Good English or Japanese communication skill.


3. Hiring: Analog & AMS IC Layout

1+ years of experience with analog Integrated Circuit (IC) layout.
Familiar with layout of analog and mixed signal circuits such as bandgap references, operational amplifiers, comparators, regulator.
Have a good understanding of analog layout concepts for deep sub-micron processes and knowledge of fabrication process.
Have experience in using Cadence Virtuoso and the Calibre LVS and DRC checking tools.
Knowledge of layout effect (matching, parasitic effect).
Self-motivator with good problem-solving skills.
Good English or Japanese communication skill.


4. Hiring: RTL Design and Verification

2+ years of experience in Functional/Logic/RTL Design/Verification
Experience in Verilog, SystemVerilog Assertion (SVA)
Familiar with Verdi/Simvision
Experience in scripting language (CShell/Bash…)
Good knowledge of MCU is a plus
Good English or Japanese communication skill


5. HIRING: FPGA DESIGN

2+ years of experience in FPGA Design with Verilog
Experience in Image Processing or Point Cloud Processing
Experience using Intel FPGA is a plus
Good English or Japanese communication skill.


6. HIRING: DFT

・2+ years of experience in DFT
Basic knowledge about IC Design Flow
Experience in scripting language (CShell/TCL…)
Good English or Japanese communication skill.

7. HIRING: STA

2+ years of experience in STA Experience in scripting language (CShell/TCL…) Good English or Japanese communication skill.


CHÍNH SÁCH TUYỂN DỤNG

🍀Hỗ trợ: Thủ tục Visa, và 100% chi phí di chuyển.
🍀Phúc lợi: Bảo hiểm, nhà ở, khám sức khỏe, sinh hoạt, đi lại,..
🍀Lương: 300-700 man/năm, thưởng theo năng lực và kinh nghiệm.


THÔNG TIN LIÊN HỆ

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🌎Xem thêm job khác tại: https://it-jp.blogspot.com
📹Kênh Youtube: Việc làm IT tại Nhật
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